1. Field of the Invention
This invention relates to semiconductor memory devices and more particularly to flash memory devices with a high coupling ratio and a method of manufacture thereof.
2. Description of Related Art
In the current state of the art, contactless drain (buried diffusion) results in low read currents which is not suitable for high speed random access devices.
U.S. Pat. No. 5,556,799 of Hong for a "Process for Fabricating A Flash EEPROM" Hong teaches that as flash EEPROM devices are made with finer resolutions, floating gate surface areas shrink. This decreases the capacitance of the effective capacitor between the floating gate layer and the control gate layer. The unwanted decrease in effective capacitance results in a reduction in the coupling ratio, which is a parameter that describes the coupling to the floating gate of the voltage present at the control gate of the device. The poor coupling of voltage to a floating gate limits the programming and accessing speed of the flash EEPROM device.
U.S. Pat. No. 5,554,544 of Hsu shows a non-uniform gate oxide created by the field oxide. However, the method/structure differs from the present invention.
Yosiaki S. Hisamune, et al., "A High Capacitive-Coupling Ratio (HiCR) Cell For 3V Only 64 Mbit And Future Flash Memories", (1993) IEDM pp. 93-19 to 93-22 describes at page 93-19
"gate dielectrics consist of 20-nm thick thermal oxide grown on the channel region and 7.5-nm thick silicon oxynitride formed underneath the floating-gate sidewalls. The cell is designed to have ultra small tunneling regions (0.2 .mu.m.times.0.4 .mu.m) and a large floating gate area (1.4 .mu.m.times.0.4 .mu.m) in order to obtain the high capacitive-coupling ratio of 0.8. Here the capacitive coupling ratio CR.sub.E is defined by ##EQU1## "where C.sub.FG is the capacitance of the interpoly oxide-nitride-oxide (ONO) dielectrics between the control gate and the floating gate and C.sub.T is the total capacitance of the floating gate."